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19-2641; Rev 0; 10/02
KIT ATION EVALU E AILABL AV
PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
General Description Features
o Integrated Bypass PFET o 150mV Dropout at 600mA Load (Regardless of External Inductor) o Dynamically Adjustable Output from 0.4V to VBATT o Externally Fixed Output from 1.25V to 2.5V with Digitally Controlled High-Power Bypass Mode (MAX8504) o 1MHz Fixed-Frequency PWM Switching o 600mA Guaranteed Output Current o 10% to 100% Duty-Cycle Operation o Low Quiescent Current 280A (typ) in Normal Mode 3.3mA (typ) in PWM Mode 0.1A (typ) in Shutdown Mode o 12-Pin Thin QFN (4mm x 4mm, 0.8mm max Height)
MAX8500-MAX8504
The MAX8500-MAX8504 PWM DC-to-DC buck converters are optimized with integrated bypass FET (0.25 typ) to provide power to the PA in N-CDMA and W-CDMA cell phones. The devices have a low on-resistance FET to bypass the external inductor for low dropout of only 150mV at 600mA load, regardless of inductor series resistance. The supply voltage range is from 2.6V to 5.5V and the guaranteed converter output current is 600mA. The 1MHz PWM switching frequency allows for small external components. The MAX8500-MAX8503 are dynamically controlled to provide varying output voltages from 0.4V to VBATT. The LDO regulation point is slightly lower than the PWM converter such that the transition into and out of dropout is smooth, regardless of the inductor resistance. The MAX8504 is programmed for fixed 1.25V to 2.5V output with external resistors. It features a high-power bypass mode that connects the output directly to the battery. All devices are designed to achieve an output settling time of less than 30s for a full-scale change in output voltage and load current. The MAX8500-MAX8504 are available in a 12-lead 4mm x 4mm thin QFN package (0.8mm max height).
Ordering Information
PART MAX8500ETC MAX8501ETC* MAX8502ETC* MAX8503ETC TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 12 Thin QFN 12 Thin QFN 12 Thin QFN 12 Thin QFN 12 Thin QFN TOP MARK AABQ -- -- AABU AABS
Applications
N-CDMA/W-CDMA Cellular Phones Wireless PDAs and Modems
Typical Operating Circuit
INPUT 2.6V TO 5.5V 10F BATT SKIP SHDN REF 1MHz OSC PWM LDO REFIN DAC LX OUT 4.7H OUTPUT 0.4V TO VBATT 4.7F
MAX8504ETC
*Future product--contact factory for availability.
Pin Configuration
SHDN 12 SKIP 11 OUT 10
GND REF
gm
1 2 3
9
BATT BATTP LX
MAX8500- MAX8504
8 7
REFIN (FB)
COMP
PGND RC 8.2k CC 1000pF
MAX8500MAX8503 GND
4 COMP
5 BATT (HP)
6 PGND
Thin QFN 4mm x 4mm
( ) MAX8504 ONLY
________________________________________________________________ Maxim Integrated Products
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
ABSOLUTE MAXIMUM RATINGS
BATTP, BATT, OUT, SHDN, SKIP, HP, REFIN, FB to GND ....................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V REF, COMP to GND ................................-0.3V to (VBATT + 0.3V) LX Current (Note 1) .............................................................2.25A Output Short-Circuit Duration ........................................Indefinite Continuous Power Dissipation (TA = +70C) 12-Lead Thin QFN (derate 16.9mW/C above +70C) .1349mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: LX has internal clamp diodes to PGND and BATTP. Applications that forward bias these diodes should take care not to exceed the IC's package power dissipation limits.
ELECTRICAL CHARACTERISTICS
(VBATT = VBATTP = 3.6V, SHDN = SKIP = BATT, VREFIN = 1.932V (MAX8500, MAX8502), VREFIN = 1.70V (MAX8501, MAX8503), CREF = 0.22F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Input BATT Voltage Undervoltage Lockout Threshold Quiescent Current SYMBOL VBATT VUVLO IQ SKIP = GND SKIP = BATT, no switching SKIP = BATT, switching Quiescent Current in Dropout Shutdown Supply Current OUT Voltage Accuracy (MAX8500, MAX8502) OUT Voltage Accuracy (MAX8501, MAX8503) OUT Voltage-Load Regulation OUT Voltage-Line Regulation OUT Input Resistance REFIN Input Current REFIN to OUT Gain (MAX8500, MAX8502) REFIN to OUT Gain (MAX8501, MAX8503) Reference Voltage Reference Load Regulation Reference UVLO FB Voltage Accuracy (MAX8504) FB Input Current (MAX8504) P-Channel On-Resistance VFB IFB PRDS VFB = 1.3V ILX = 180mA, VBATT = 3.6V ILX = 180mA, VBATT = 2.6V IREF AV AV VREF 10A < IREF < 100 A 0.86 1.225 0.96 1.250 10 0.35 0.45 PWM buck LDO linear regulator PWM buck LDO linear regulator 1.225 MAX8500, MAX8503 100 -1 ISHDN VOUT VOUT VREFIN = 2.2V (MAX8500, MAX8503), HP = BATT (MAX8504) SHDN = GND, VBATT = VBATTP = 5.5V VREFIN = 1.932V, load = 0 to 600mA VREFIN = 0.227V VREFIN = 1.700V, load = 0 to 600mA VREFIN = 0.200V 3.33 0.35 3.33 0.35 CONDITIONS VBATT rising, 1% hysteresis MIN 2.6 2.15 TYP 2.35 280 450 3300 400 0.1 3.40 0.40 3.40 0.40 -0.05 0.007 245 0.1 1.76 1.68 2 1.909 1.25 1.275 6.25 1.10 1.275 150 0.70 +1 700 5 3.47 0.45 3.47 0.45 A A V V %/A %/V k A V/V V/V V mV V V nA MAX 5.5 2.50 450 2200 A UNITS V V
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
ELECTRICAL CHARACTERISTICS (continued)
(VBATT = VBATTP = 3.6V, SHDN = SKIP = BATT, VREFIN = 1.932V (MAX8500, MAX8502), VREFIN = 1.70V (MAX8501, MAX8503), CREF = 0.22F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER N-Channel On-Resistance LDO/Bypass P-Channel On-Resistance P-Channel Current-Limit Threshold N-Channel Current-Limit Threshold P-Channel Pulse-Skipping Current Threshold LDO/Bypass P-Channel Current-Limit Threshold LX RMS Current LX Leakage Current Maximum Duty Cycle Minimum Duty Cycle COMP Clamp Low Voltage COMP Clamp High Voltage MAX8500, MAX8501 Transconductance Current-Sense Transresistance Internal Oscillator Frequency LOGIC INPUTS (SHDN, HP, SKIP) Logic Input High Logic Input Low Logic Input Current THERMAL SHUTDOWN Thermal-Shutdown Temperature Thermal-Shutdown Hysteresis 160 15 C C VIH VIL 0.1 1.6 0.4 1.0 V V A gm RCS fOSC 0.8 MAX8502, MAX8503 MAX8504 SKIP = GND SKIP = BATT 0.7 2.0 85 75 150 10 1.0 2.3 142 125 250 0.38 1.0 1.2 (Note 3) VBATT = VBATTP = 5.5V, VLX = 0 to 5.5V -20 100 0 13 1.1 2.4 200 175 350 V/A MHz S +0.1 ILIMP ILIMN ISKIP SKIP = BATT SKIP = GND SKIP = GND SYMBOL NRDS CONDITIONS ILX = 180mA, VBATT = 3.6V ILX = 180mA, VBATT = 2.6V IOUT = 180mA, VBATT = 3.6V IOUT = 180mA, VBATT = 2.6V 1.30 -0.80 30 118 0.70 MIN TYP 0.26 0.33 0.25 0.3 1.45 -0.60 47 148 1.00 1.60 -0.40 65 178 1.55 1.5 +20 0.60 MAX 0.60 UNITS A A mA mA A A A % % V V
MAX8500-MAX8504
Note 2: Specifications to -40C are guaranteed by design and not subject to production test. Note 3: Guaranteed by design, not production tested.
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
Typical Operating Characteristics
(VBATT = 3.6V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT VOLTAGE IN NORMAL MODE
MAX8500 toc01
EFFICIENCY vs. OUTPUT VOLTAGE IN PWM MODE
RLOAD = 10 90 EFFICIENCY (%) RLOAD = 5 80 RLOAD = 15 70
MAX8500 toc02
EFFICIENCY vs. INPUT VOLTAGE
MAX8500 toc03
100 RLOAD = 10 90 EFFICIENCY (%) RLOAD = 5 80 RLOAD = 15
100
100
90 EFFICIENCY (%) VOUT = 1.5V VOUT = 3.4V
80
70
70 VOUT = 0.4V SKIP = GND RLOAD = 10 50
60 SKIP = GND 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V)
60 SKIP = BATT 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V)
60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
EFFICIENCY vs. LOAD CURRENT
VOUT = 2.5V; NORMAL MODE
MAX8500 toc04
MAX8500/MAX8503 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8500 toc05
MAX8504 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8500 toc06
100
300 250 DROPOUT VOLTAGE (mV) 200 150 100 50 0 VOUT = 2.5V VOUT = 3.4V
0.25
90 EFFICIENCY (%)
0.20 DROPOUT VOLTAGE (V)
80 VOUT = 1.5V; PWM 70 VOUT = 1.5V; NORMAL MODE 60 VOUT = 2.5V; PWM 50 1 10 100 1000 LOAD CURRENT (mA)
0.15
0.10
0.05 VOUT = 3.5V HP = BATT 0 0 100 200 300 400 500 600 700 800 900 1000 LOAD CURRENT (mA) 0 100 200 300 400 500 600 700 800 900 1000 LOAD CURRENT (mA)
MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION
MAX8500 toc07
MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION
MAX8500 toc08
MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION
MAX8500 toc09
3.55 3.50 OUTPUT VOLTAGE (V) 3.45 3.40 3.35 3.30 3.25 3.20 3.15 RLOAD = 10 RLOAD = 7.6 RLOAD = 5 L = SUMIDA CDRH3D16-4R7M RLOAD = 15 VBATT
3.55 3.50 OUTPUT VOLTAGE (V) 3.45 3.40 3.35 3.30 3.25 3.20 3.15 VBATT RLOAD = 15 RLOAD = 10 RLOAD = 7.6 RLOAD = 5 L = TOKO D312F-4R7M
3.50 3.45 OUTPUT VOLTAGE (V) 3.40 3.35 3.30 3.25 3.20 0
VOUT = 3.4V; SKIP = BATT 300 600 900 1200 1500
3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 VBATT (V)
3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 VBATT (V)
LOAD CURRENT (mA)
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
Typical Operating Characteristics (continued)
(VBATT = 3.6V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE IN PWM MODE
MAX8500 toc10
SUPPLY CURRENT vs. SUPPLY VOLTAGE IN NORMAL MODE
900 SUPPLY CURRENT (A) 800 700 600 500 400 300 VOUT = 1.5V VOUT = 3.4V SKIP = GND
MAX8500 toc11
HEAVY-LOAD SWITCHING WAVEFORM
MAX8500 toc12
6 5 SUPPLY CURRENT (mA) 4 VOUT = 1.5V 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOUT = 0.4V SKIP = BATT
1000
VLX 2V/div
200 5.5 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V)
VOUT = 0.4V 4.0 4.5 5.0 5.5
VIN = 3.6V, VOUT = 3.3V LOAD = 10 400ns/div
VOUT AC-COUPLED 2mV/div
SUPPLY VOLTAGE (V)
MEDIUM-LOAD SWITCHING WAVEFORM
MAX8500 toc13
LIGHT-LOAD SWITCHING WAVEFORM IN PWM MODE
MAX8500 toc14
LIGHT-LOAD SWITCHING WAVEFORM IN SKIP MODE
MAX8500 toc15
VLX 2V/div
VLX 2V/div
VLX 2V/div VIN = 3.6V, VOUT = 0.4V LOAD = 10 VOUT AC-COUPLED 20mV/div
VOUT AC-COUPLED 5mV/div VIN = 3.6V, VOUT = 1.5V LOAD = 10 400ns/div VIN = 3.6V, VOUT = 0.4V LOAD = 10 400ns/div
VOUT AC-COUPLED 5mV/div
2s/div
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
Typical Operating Characteristics (continued)
(VBATT = 3.6V, TA = +25C, unless otherwise noted.)
EXITING AND ENTERING SHUTDOWN
MAX8500 toc16
REFIN TRANSIENT RESPONSE
MAX8500 toc17
SHDN 2V/div
REFIN 1V/div
SKIP = BATT VOUT 2V/div SKIP = GND VIN = 3.6V, LOAD = 10, REFIN = 0.455 TO 1.932V 20s/div
VOUT 1V/div
VIN = 3.6V, VOUT = 3.4V LOAD = 10 100s/div
HP TRANSIENT RESPONSE
MAX8500 toc18
LINE-TRANSIENT RESPONSE
MAX8500 toc19
HP 1V/div
VOUT AC-COUPLED 10mV/div VIN = 3.5V TO 4.5V, VOUT = 1.5V LOAD = 10,
VIN = 3.6V, LOAD = 10, HP = 0 TO 1.8V SKIP = GND VOUT 1V/div SKIP = BATT
VIN 500mV/div
20s/div
100s/div
ENTERING AND EXITING DROPOUT
MAX8500 toc20
VOUT AC-COUPLED 200mV/div
VIN = 3.8V TO 3.4V TO 3.8V, VOUT = 3.4V, LOAD = 600mA VIN 200mV/div
100s/div
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
Pin Description
PIN MAX8500- MAX8503 1 2 3 MAX8504 1 2 -- NAME GND REF REFIN Ground Reference Bypass Pin. Connect a 0.22F ceramic capacitor from this pin to GND. External Reference Input. Connect REFIN to the output of a DA converter for dynamic adjustment of the output voltage. Output Feedback Sense Input. To set the output voltage, connect FB to the center of an external resistive voltage-divider between OUT and GND. FB voltage regulates to 1.25V when HP is logic 0. Compensation. Connect a series resistor and capacitor from this pin to GND to stabilize the regulator (see the Compensation, Stability, and Output Capacitor section). IC Supply Voltage Input. Connect to BATTP. High-Power Bypass Mode. Connect to GND or logic 0 for OUT to regulate to the voltage set by the external resistors on FB. Drive with logic 1 for OUT to be connected to BATT through the internal bypass PFET. Power Ground Inductor Connection to the Drains of the Internal Power MOSFETs. High impedance in shutdown mode. Power-Supply Voltage Input. Connect to a 2.6V to 5.5V source. Bypass with a low-ESR 10F capacitor. Regulator Output. Connect OUT directly to the output voltage. Skip Control Input. Connect to GND or logic 0 for normal mode. Connect to BATT or logic 1 for forced-PWM mode. Shutdown Control Input. Connect to GND or logic 0 for shutdown mode. Connect to BATT or logic 1 for normal operation. FUNCTION
MAX8500-MAX8504
--
3
FB
4 5, 9 -- 6 7 8 10 11 12
4 9 5 6 7 8 10 11 12
COMP BATT HP PGND LX BATTP OUT SKIP SHDN
Detailed Description
The MAX8500-MAX8504 PWM step-down DC-to-DC converters with integrated bypass PFET are optimized for low-voltage, battery-powered applications where high efficiency and small size are priorities (such as linear PA applications). An analog control signal dynamically adjusts the MAX8500-MAX8503s' output voltage from 0.4V to VBATT with a settling time <30s (Figure 1). The MAX8504 uses external feedback resistors to set the output voltage from 1.25V to 2.5V. The MAX8500-MAX8504 operate at a high 1MHz switching frequency that reduces external component
size. Each device includes an internal synchronous rectifier that provides for high efficiency and eliminates the need for an external Schottky diode. The normal operating mode uses constant-frequency PWM switching at medium and heavy loads, and automatically pulse skips at light loads to reduce supply current and extend battery life. An additional forced-PWM mode switches at a constant frequency, regardless of load, to provide a well-controlled spectrum in noise-sensitive applications. Battery life is maximized by low-dropout operation at 100% duty cycle and a 0.1A (typ) logic-controlled shutdown mode.
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
INPUT 2.6V TO 5.5V 10F BATT SKIP SHDN REF 1MHz OSC PWM LDO REFIN DAC LX OUT 4.7H OUTPUT 0.4V TO VBATT 4.7F
gm
COMP
PGND RC 8.2k CC 1000pF
MAX8500MAX8503 GND
Figure 1. MAX8500-MAX8503 Functional Diagram and Typical Operating Circuit
PWM Control
The MAX8500-MAX8504 use a fixed-frequency, currentmode, PWM controller capable of achieving 100% duty cycle. Current-mode feedback provides cycle-by-cycle current limiting, superior load and line response, as well as overcurrent protection for the internal MOSFET and rectifier. A comparator at the P-channel MOSFET switch detects overcurrent at 1.5A. During PWM operation, the MAX8500-MAX8504 regulate output voltage by switching at a constant frequency and then modulating the duty cycle with PWM control. The error-amp output, the main switch current-sense signal, and the slope compensation ramp are all summed using a PWM comparator. The comparator modulates the output power by adjusting the peak inductor current during the first half of each cycle based on the output error voltage. The MAX8500-MAX8504 have relatively low AC loop gain coupled with a high gain integrator to enable the use of a small, low-valued output filter capacitor. The resulting load regulation is 0.03% at 0 to 600mA.
Normal Mode Operation
Connecting SKIP to GND enables normal operation. This allows automatic PWM control at medium and heavy loads and skip mode at light loads to improve efficiency and reduce quiescent current to 280A. Operating in normal mode also allows the MAX8500-MAX8504 to pulse skip when the peak inductor current drops below 148mA, corresponding to a load current of approximately 75mA. During skip operation, the MAX8500-MAX8504 switch only as needed to service the load, reducing the switching frequency and associated losses in the internal switch and synchronous rectifier. There are three steady-state operating conditions for the MAX8500-MAX8504 in normal mode. The device performs in continuous conduction for heavy loads in a manner identical to forced-PWM mode. The inductor current becomes discontinuous at medium loads, requiring the synchronous rectifier to be turned off before the end of a cycle as the inductor current reaches zero. The device enters into skip mode when the converter output voltage exceeds its regulation limit before the inductor current reaches its skip threshold level. During skip mode, a switching cycle initiates when the output voltage has dropped out of regulation. The P-channel MOSFET switch turns on and conducts cur-
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
rent to the output filter capacitor and load until the inductor current reaches the skip peak current limit. Then the main switch turns off, and the magnetic field in the inductor collapses, while current flows through the synchronous rectifier to the output filter capacitor and the load. The synchronous rectifier is turned off when the inductor current reaches zero. The MAX8500-MAX8504 wait until the skip comparator senses a low output voltage again. Dropout voltage at 100% duty cycle is the output current multiplied by the sum of the internal PMOS on-resistance (0.35 typ) and the inductor resistance. Once the output voltage drops by 5%, the PFET bypass LDO (MAX8500-MAX8503) turns on and reduces the dropout voltage. The dropout in the bypass PFET equals the load current multiplied by the on-resistance (0.25 typ) in parallel with the buck converter and inductor dropout resistance.
MAX8500-MAX8504
Forced-PWM Operation
Connect SKIP to BATT for forced-PWM operation. Forced-PWM operation is desirable in sensitive RF and data-acquisition applications to ensure that switching harmonics do not interfere with sensitive IF and datasampling frequencies. A minimum load is not required during forced-PWM operation since the synchronous rectifier passes reverse-inductor current as needed to allow constant-frequency operation with no load. ForcedPWM operation uses higher supply current with no load (3.3mA typ) compared to skip mode (280A typ).
Undervoltage Lockout (UVLO)
The MAX8500-MAX8504 do not operate with battery voltages below the UVLO threshold of 2.35V (typ). The output remains off until the supply voltage exceeds the UVLO threshold. This guarantees the integrity of the output voltage regulation.
Synchronous Rectification
An N-channel, synchronous rectifier operates during the second half of each switching cycle (off-time). When the inductor current falls below the N-channel current comparator threshold or when the PWM reaches the end of the oscillator period, the synchronous rectifier turns off. This prevents reverse current from the output to the input in pulse-skipping mode. During PWM operation, the ILIMN threshold adjusts to permit reverse current during light loads. This allows regulation with a constant switching frequency and eliminates minimum load requirements for fixed-frequency operation.
100% Duty-Cycle Operation and Dropout
The maximum on-time can exceed one internal oscillator cycle, which permits operation at 100% duty cycle. Near dropout, cycles may be skipped, reducing switching frequency. However, voltage ripple remains small because the current ripple is still low. As the input voltage drops even further, the duty cycle increases until the internal P-channel MOSFET stays on continuously.
INPUT 2.6V TO 5.5V 10F BATT SKIP SHDN REF PWM LX
4.7H
OUTPUT 1.25V TO 2.5V OR VBATT 4.7F
OUT OVERCURRENT PROTECTION
1MHz OSC HP COMP PGND RC 9.1k CC 560pF GND gm 1.25V
FB
Figure 2. MAX8504 Functional Diagram and Typical Operating Circuit _______________________________________________________________________________________ 9
PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
High-Power Bypass Mode (MAX8504)
A high-power bypass mode is available on the MAX8504 for use when a PA transmits at high power. This mode connects OUT to BATT through the bypass PFET. Additionally, the PWM buck converter is forced into 100% duty cycle to further reduce dropout.
3.4 WCDMA PA SUPPLY VOLTAGE (V) 3.0
Shutdown Mode
Driving SHDN to GND places the MAX8500-MAX8504 in shutdown mode. In shutdown, the reference, control circuitry, internal switching MOSFET, and synchronous rectifier turn off and the output becomes high impedance. Input current falls to 0.1A (typ) during shutdown mode. Drive SHDN high for normal operation.
1.0 0.4 0 0 30 300 W-CDMA PA SUPPLY CURRENT (mA) 600
Current-Sense Comparators
The MAX8500-MAX8504 use several internal currentsense comparators. In PWM operation, the PWM comparator terminates the cycle-by-cycle on-time and provides improved load and line response. A second current-sense comparator used across the P-channel switch controls entry into skip mode. A third currentsense comparator monitors current through the internal N-channel MOSFET to prevent excessive reverse currents and determine when to turn off the synchronous rectifier. A fourth comparator used at the P-channel MOSFET detects overcurrent. A fifth comparator used at the bypass/LDO P-channel MOSFET detects overcurrent in the HP mode or at dropout. This protects the system, external components, and internal MOSFETs under overload conditions.
Figure 3. Typical W-CDMA Power Amplifier Load Profile
LX
MAX8504
FB
R1
R2 50k
Applications Information
Setting the Output Voltage
Using a DAC (MAX8500-MAX8503) The MAX8500-MAX8503 are optimized for highest system efficiency when applying power to a linear PA in CDMA handsets. When transmitting at less than full power, the supply voltage to the PA is lowered from VBATT to as low as 0.4V to greatly reduce battery current. Figure 3 shows the typical CDMA PA load profile. The use of DC-to-DC converters such as the MAX8500- MAX8503 dramatically extends talk time in these applications. The MAX8500-MAX8503s' output voltage is dynamically adjustable from 0.4V to VBATT by the use of the REFIN input. The gain from VREFIN to VOUT is internally set to 1.76X (MAX8500 and MAX8502) or 2X (MAX8501 and MAX8503). VOUT can be adjusted during operation by
Figure 4. Setting the Adjustable Output Voltage
driving REFIN with an external DAC. The MAX8500- MAX8503 output responds to full-scale change in voltage and current in <30s. Using External Divider (MAX8504) The MAX8504 is intended for two-step VCC control applications where high efficiency is a priority. Select an output voltage between 1.25V and VBATT by connecting FB to a resistive divider between the output and GND (Figure 4). Select feedback resistor R2 in the 5k to 50k range. R1 is then given by: V R1 = R2 x OUT - 1 VFB where VFB = 1.25V.
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
Input Capacitor Selection
Capacitor ESR is a major contributor to input ripple in high-frequency DC-to-DC converters. Ordinary aluminum electrolytic capacitors have high ESR and should be avoided. Low-ESR tantalum capacitors or polymer capacitors are better and provide a compact solution for space-constrained surface-mount designs. Ceramic capacitors have the lowest ESR overall. The input filter capacitor reduces peak currents and noise at the input voltage source. Connect a low-ESR bulk capacitor (10F typ) to the input. Select this bulk capacitor to meet the input ripple requirements and voltage rating rather than capacitance value. Use the following equation to calculate the maximum RMS input current: I IRMS = OUT x VIN VOUT x ( VIN - VOUT ) to the left. System stability requires that the compensation zero must be placed to ensure adequate phase margin (at least 30 at unity gain). See Figures 1 and 2 for RC and CC recommended values.
MAX8500-MAX8504
Inductor Selection
A 4H to 6H inductor is recommended for most applications. For best efficiency, the inductor's DC resistance should be <400m. Saturation current (ISAT) should be greater than the maximum DC load at the PA's supply plus half the inductor current ripple. Twostep V CC applications typically require very small inductors with ISAT in the 200mA to 300mA region. See Table 1 and Table 2 for recommended inductors and manufacturers.
PC Board Layout and Routing
High switching frequencies and large peak currents make PC board layout a very important part of design. Good design minimizes EMI, noise on the feedback paths, and voltage gradients in the ground plane, all of which can result in instability or regulation errors. Connect the inductor, input filter capacitor, and output filter capacitor as close together as possible and keep their traces short, direct, and wide. Connect their ground pins at a single common node in a star ground configuration. The external voltage-feedback network should be very close to the FB pin, within 0.2in (5mm). Keep noisy traces, such as those from the LX pin, away from the voltage-feedback network. Position the bypass capacitors as close as possible to their respective pins to minimize noise coupling. For optimum performance, place input and output capacitors as close to the device as possible. Connect GND and PGND directly under the IC to the exposed paddle. The MAX8504 evaluation kit manual illustrates an example PC board layout and routing scheme.
Compensation, Stability, and Output Capacitor
The MAX8500-MAX8504 are externally compensated by placing a resistor and a capacitor (see Figures 1 and 2, RC and CC) in series from COMP to GND. An additional capacitor (Cf) may be required from COMP to GND if high-ESR output capacitors are used. The capacitor integrates the current from the transconductance amplifier, averaging output capacitor ripple. This sets the device speed for transient response and allows the use of small ceramic output capacitors because the phase-shifted capacitor ripple does not disturb the current-regulation loop. The resistor sets the proportional gain of the output error voltage by a factor gm RC. Increasing this resistor also increases the sensitivity of the control loop to output ripple. The resistor and capacitor set a compensation zero that defines the system's transient response. The load creates a dynamic pole, shifting in frequency with changes in load. As the load decreases, the pole frequency shifts
Chip Information
TRANSISTOR COUNT: 2530 PROCESS: BiCMOS
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11
PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
Table 1. Suggested Inductors
MANUFACTURER Murata Sumida Taiyo Yuden Toko PART NO. LQH3C CDRH2D18 LBLQ2016 D312F INDUCTANCE (H) 4.7 4.7 4.7 4.7 ESR (m) 200 63 250 320 SATURATION CURRENT (A) 0.45 0.63 0.21 0.83 DIMENSIONS (mm) 2.5 x 3.2 x 2 3.2 x 3.2 x 2 1.6 x 2 x 1.6 3.6 x 3.6 x 1.2
Table 2. Manufacturers of Suggested Components
MANUFACTURER Murata Sumida Taiyo Yuden Toko PHONE 770-436-1300 847-956-0666 (USA) 81-3-3607-5111 (Japan) 408-573-4150 847-297-0070 WEBSITE www.murata.com www.sumida.com www.t-yuden.com www.tokoam.com
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PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
MAX8500-MAX8504
21-0139
A
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13
PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets MAX8500-MAX8504
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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